1. Field of the Invention
This invention relates to a semiconductor memory device. More particularly, this invention relates to, for example, a nonvolatile semiconductor memory device including MOS transistor having a floating gate and a control gate.
2. Description of the Related Art
Nonvolatile semiconductor memories, including NOR flash memories and NAND flash memories, have been widely used.
In recent years, a flash memory combining the best features of the NOR flash memory and the NAND flash memory has been proposed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. This flash memory has memory cells, each including two MOS transistors. In such a memory cell, one MOS transistor functioning as a nonvolatile memory section has a structure including a control gate, and a floating gate and is connected to a bit line. The other MOS transistor, which is connected to a source line, is used to select a memory cell.
With the conventional flash memory, the address decode signal obtained by decoding the address signal is raised to a specific potential by a level shift circuit. Thereafter, the raised signal is supplied to a select gate line. Since the level shift circuit in the conventional flash memory has a low operating speed, the operating speed of the flash memory tends to be low.